1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and especially relates to a structure and manufacturing method of a split gate nonvolatile memory.
2. Description of the Related Art
The floating gate memory, which incorporates floating gate transistors as memory cells, is a sort of nonvolatile semiconductor memory devices which store data even when the power supply is shut off. Programming data in to the cell is achieved by injecting electric charges into the floating gate, and erasing data is achieved by pulling electric charges off the floating gate. Data program operation causes an increase in the threshold voltage of the floating-gate transistor cell and prevents a drain current from flowing through the floating-gate transistor in read operation. Data erase operation causes a decrease in the threshold voltage of the floating-gate transistor cell, and allows a drain current to flow through the floating-gate transistor in reading operation.
Data erase operation must be implemented so that the threshold voltage of the cell is kept in a predetermined range. When the threshold voltage of the cell is excessively reduced due to “over erasing”, the operation of the floating-gate nonvolatile memory may suffer from unstable operation, because the drain current may flow through the cell even when the read voltage is not applied to the control gate.
The split gate nonvolatile memory is known as a floating-gate nonvolatile memory which effectively avoids the problem resulting from the over erasing, as disclosed in Japanese Laid-Open Patent Application No. Jp-A Heisei 9-92734 (hereinafter, the '734 application).
FIG. 1 is a cross section view showing the structure of a typical split gate nonvolatile memory 101. In the conventional split gate nonvolatile memory 101, a first diffusion region 103 and a second diffusion region 104 are formed within a substrate 102.
The first diffusion region 103 is used as a drain in program operation, while used as a source in read operation. The second diffusion region 104, on the other hand, is used as a source in program operation, while used as a drain in read operations. A channel region 110, in which a channel is formed, is provided between the first and second diffusion regions 103 and 104. In the split gate nonvolatile memory 101, a floating gate 106 is opposed to only a part of the channel region 110 (referred to as the first channel region 110a, hereinafter), and a control gate 108 is opposed to another part of the channel region (referred to as the second channel region 110b, hereinafter), differently from a stack gate nonvolatile memory cell. The floating gate 106 and the first channel region 110a function as a memory transistor, while the control gate 108 and the second channel region 110b functions as a selection transistor.
As described above, the channel region 110 includes the first and second channel regions 110a and 110b. The first channel region 110a is positioned under the floating gate 106 across a gate oxide film 105. The second channel region 110b is positioned under the control gate 108 across a tunnel oxide film 107. In addition, the tunnel oxide film 107 is formed so as to cover the upper and side faces of the floating gate 106, and the control gate 108 is formed to cover the floating gate 106 across the tunnel oxide film 107. In other words, the control gate 108 is opposed to the side and upper faces of the floating gate 106 across the tunnel oxide film 107.
A channel is formed within the first channel region 110a under the floating gate 106 in accordance with the voltage applied to the control gate 108 and the amount of charges accumulated in the floating gate 106. In the similar way, a channel is formed within the second channel region 110b in accordance with the voltage applied to the control gate 108.
Various techniques are known for erasing data in a memory cell within the conventional split gate nonvolatile memory. One known technique involves flowing an FN (Fowler-Nordheim) tunnel current from the control gate to the floating gate to thereby pull electric charges from the floating gate to the control gate. One advantage of the split gate nonvolatile memory is that the channel can be turned off by controlling the control gate, even when electric charges are excessively pulled off the floating gate (that is, even when over erasing occurs). The split gate nonvolatile memory effectively avoids the problem that the drain current may flow through the cell even when the read voltage is not applied to the cell.
Another advantage is that the split gate nonvolatile memory is adapted to the source side injection (SSI), due to the structure in which the control gate is laterally positioned adjacent to the floating gate. The source side injection is superior in the injection efficiency of channel hot electrons to the conventional channel hot electron injection from the drain side (often referred to as the drain side injection), achieving high speed program operation.
FIGS. 2A to 2C are cross section views showing an exemplary operation of the above-mentioned split gate nonvolatile memory 101. FIG. 2A shows an exemplary write operation of the split gate nonvolatile memory 101, and FIG. 2B shows an exemplary erase operation. Finally, FIG. 2C shows an exemplary read operation of the split gate nonvolatile memory 101. Referring to FIG. 2A, the first diffusion region 103 is used as the drain and pulled up to a voltage higher than that of the second diffusion region 104, which is used as the source, when data program operation is performed in the split gate nonvolatile memory 101. This causes generation of hot electrons (electrons with high energy) in the source-side portion of the channel under the floating gate 106 and data is programmed into the cell by injecting the hot electrons into the floating gate 106 through the gate oxide film 105. The floating gate 106 is negatively charged after the write operation.
Referring to FIG. 2B, data erase operation is performed by pulling electrons from the floating gate 106 to the control gate 108 through the tunnel oxide film 107 by using tunneling. The floating gate 106 is positively charged after the erase operation.
Referring to FIG. 2C, a predetermined read voltage is applied to the control gate 108 to activate the memory transistor, when data read operation is performed in the split gate nonvolatile memory 101. The source-drain current varies depending on the amount of electrons injected into the floating gate 106, and the data stored in the cell is identified from the source-drain current.
The threshold voltage of the cell is dependent on the dopant concentration of the channel region 110. When the dopant concentration of the channel region 110 is excessively high, the threshold voltage of the selection transistor within the cell is excessively increased, resulting in the reduced current drive ability of the selection transistor. This may cause a problem in read operation. When the dopant concentration of the channel region 110 is excessively low, this may cause reduced efficiency in program operation. The low dopant concentration of the channel region 110 implies that the dopant concentration of the portion of the channel region 110 opposed to the spacing between the floating gate 106 and the control gate 108. This causes the decrease in the electric field strength at the spacing portion in program operation.
The '734 application also discloses the dopant implantation into the channel region 110. FIG. 3A to 3C illustrates the process of the dopant implantation disclosed in the '734 application. As shown in FIG. 3A, the disclosed dopant implantation process begins with implanting P-type dopants (such as boron) into a surface portion of a substrate 102 with a predetermined dopant concentration. A first polysilicon film 111 is then deposited to cover the entire structure through a CVD method.
As shown in FIG. 3B, a resist 121 is then formed on the first polysilicon film 111. This is followed by removing a portion of the first polysilicon film 111 with the resist 121 used as a mask to thereby form an opening exposing a target region of the substrate 102. The region of the substrate 102 which remains covered with the first polysilicon film 111 is used as the first channel region 110a. N-type dopants (such as phosphorus) are then implanted into the substrate 102 through the opening to achieve counter-ion implantation. The N-type dopants are implanted so as not to convert the conductivity type of the target region of the substrate 102 from P-type to N-type. The target region, into which the N-type dopants are implanted, has a reduced effective P-type dopant concentration and is used as the second channel region 110b. 
This is followed by forming an oxide film 107, as shown in FIG. 3C. Subsequently, as shown in FIG. 3D, a second polysilicon film 112 is deposited to cover entire structure by using a CVD method.
As describe above, the disclosed dopant implantation process uses a counter-dopant implantation technique to form the first and second channel regions 110a and 110b so that the first and second channel regions 110a and 110b have different dopant concentrations. This achieves increasing the electric field at the vicinity of the first diffusion region 103 in program operation and improving the current drive ability in read operation.
U.S. Pat. No. 6,525,371 discloses a split gate nonvolatile memory having a configuration different from that of the above mentioned split gate nonvolatile memory 101. FIG. 4 is a cross section view showing the structure of the disclosed split gate nonvolatile memory device, which is referred to as the split gate nonvolatile memory 201, hereinafter. The split gate nonvolatile memory 201 includes first and second diffusion regions 203 and 204 formed within a substrate 202. The split gate nonvolatile memory 201 additionally includes a floating gate 205 and a control gate 206. The floating gate 205 is positioned over the substrate 202 across a gate oxide film 207. The control gate 206 is positioned over the substrate 202 across a tunnel oxide film 208. The tunnel oxide film 208 extends to the space between the floating gate 205 and the control gate 206.
One of the recent requirements imposed on the split gate nonvolatile memory is higher storage capacity, and therefore, cell size reduction is strongly required. One possible approach is reduction in the gate length of the transistor within the memory cell. For the split-gate nonvolatile memory, the gate length of the floating gate is desired to be reduced.
However, the reduction of the floating gate length may cause severe short channel effect and punch through. The excessive reduction in the floating gate length may cause an excessive decrease in the threshold voltage of the memory transistor, due to the short channel effect. Additionally, the excessive reduction in the floating gate length may result in that the source-side depletion layer reaches the drain-side depletion layer and may make the current through the memory cell uncontrollable.
FIG. 5 is a cross section view that schematically illustrates write operation of the memory cell with an excessively-short floating gate length in the sprit-gate nonvolatile memory 201. Due to the excessively-short floating gate length, the source-side depletion layer may be expanded to cause punch through in write operation, during which a high voltage is applied to the first diffusion layer 203.
When a source-side injection technique is used to inject electrons into the floating gate during program operation, the sprit gate nonvolatile memory 201 requires concentrating an electric field into the substrate portion opposed to the spacing between the floating gate 205 and the control gate 206 in order to generate a desired amount of hot electrons; however, punch through undesirably prevents concentration of the electric field into the desired substrate portion, and interferes the generation of a desired amount of channel hot electrons. As a result, the punch through may cause reduction of the programming efficiency or failure of program operation.
Increase in the dopant concentration in the substrate under the floating gate may effectively suppress the punch through, resulting in successfully injecting a desired amount of hot electrons into the floating gate of a selected cell; however, the increase in the dopant concentration under the floating gate may cause Avalanche breakdown, reducing the withstand voltage of the PN junction formed between the substrate and the diffusion regions 203 and 204. The increase in the dopant concentration in the substrate reduces the width of the depletion layer between the diffusion region and the substrate. An Avalanche breakdown may occur, when a high reverse voltage is applied to a PN junction with a reduced depletion layer width.
Another issue is that the increase in the dopant concentration may also cause undesirable programming of an unselected cell in program operation. In program operation, a high voltage is to be applied to the source of a selected memory cell. This causes that the high voltage is also applied to sources of unselected memory cells, because one source is usually shared by multiple cells in a sprit gate nonvolatile memory.
FIG. 6 illustrates the operation of an unselected cell in program operation. A high voltage is fed to the first diffusion region 203 of the unselected cell to reversely bias the PN junction between the substrate 202 and the first diffusion region 203. Due to the decrease in the breakdown voltage of the PN junction resulting from the increase in the dopant concentration of the substrate, the junction leak current is increased between the substrate 202 and the first diffusion region 203 and this enhances the generation of hot electrons. The generated hot electrons are injected into the floating gate 205, jumping over the energy barrier of the gate oxide film 207, by the potential difference between the floating gate 205 and the substrate 202. Such phenomenon is often referred to as the substrate hot electron injection. As thus described, the split gate nonvolatile memory suffers from the substrate hot electron injection into the floating gate 205 of the unselected cell which causes undesirable programming of the unselected cell, when the dopant concentration of the substrate is excessively increased in the portion near the first diffusion region 203.